Technical Field
Embodiments of the disclosure relate to a display device capable of driving at low speed.
Discussion of the Related Art
Display devices have been used in various display units, such as portable information devices, office devices, computers, and televisions.
Methods for reducing power consumption of the display device include low speed driving technology. The low speed driving technology is to change a frame frequency (e.g., a driving frequency) based on a change in the amount of data. In a stop image, in which there is no change of data, the low speed driving technology refreshes the screen of the display device using a frame frequency less than an input frame frequency (for example, a normal frame frequency of 60 Hz). In a moving image in which there is a change in data, the screen of the display device is refreshed using a normal driving method based on the input frame frequency. The display device may change the frame frequency in response to a panel self refresh (PSR) control signal received from a system. For example, when the PSR control signal is input at an on-level in conformity with the stop image, the display device may reduce the frame frequency to a frequency less than 60 Hz. Further, when the PSR control signal is input at an off-level in conformity with the moving image, the display device may keep the frame frequency at 60 Hz.
The low speed driving technology may be implemented through an interlaced driving scheme. In the interlaced low speed driving scheme, one frame is time-divided into a plurality of sub-frames, and gate lines are interlace-driven in each sub-frame. In the interlaced driving scheme, as the number of sub-frames increases, a length of one frame increases. Hence, the frame frequency is reduced. As the frame frequency gradually decreases from 60 Hz for the low speed drive, a data transition frequency (used in the supply of a data voltage) of a source driver decreases. Hence, power consumption is reduced.
As shown in FIG. 2, the display device adopting the interlaced low speed driving scheme may design a connection structure of pixels in a Z-inversion scheme and may control polarities of data voltages output from a source driver in a column inversion scheme, as a method for reducing power consumption. In FIG. 2, reference numerals D1 to D5 denote data lines to which the data voltage is supplied, and reference numerals G1 to G4 denote gate lines to which a scan pulse is supplied. In the pixel connection structure of the Z-inversion scheme, each of the pixels on odd-numbered display lines may be connected to the data line through a thin film transistor (TFT) and may be disposed on the right side of the data line, and each of the pixels on even-numbered display lines may be connected to the data line through the TFT and may be disposed on the left side of the data line. The source driver increases a polarity inversion period of the data voltage output through one output channel to one frame using the column inversion scheme, as illustrated by polarity reversals D1(−), D2(+), D3(−), and so on. Thus, the pixels, which are disposed in a zigzag shape based on the same data line (for example, D2) in a vertical direction, receive the data voltage of the same polarity. The display device may reduce the power consumption while controlling a display polarity in a dot inversion scheme based on the pixel connection structure and a polarity control method of the data voltage.
The related art display device has the following problems.
First, in the related art display device, when a normal driving mode is converted into an interlaced low speed driving mode and vice versa while displaying the same pattern of a single color, the data transition changes due to a difference between the driving modes. Hence, a luminance deviation is perceived. For example, as shown in FIG. 3A, when a green pattern is displayed in 60 Hz normal driving mode (as indicated by the non-hashed portions of the subframes corresponding to the G subpixel), the data voltage supplied through the data lines D2 and D5 alternately has a white gray level and a black gray level in a cycle of one horizontal period. On the other hand, as shown in FIG. 3B, when a green pattern is displayed in 30 Hz interlaced low speed driving mode (as indicated by the non-hashed portions of the subframes corresponding to the G subpixel), the data voltage supplied through the data lines D2 and D5 is kept at the white gray level (+) during a first sub-frame period and then is kept at the black gray level (Vcom) during a second sub-frame period. In FIGS. 3A and 3B, the white gray level is represented by a white pattern, and the black gray level is represented by an oblique line pattern. Because the transition number of data in FIG. 3B is less than the transition number of data in FIG. 3A, a charge amount of data in FIG. 3B is more than a charge amount of data in FIG. 3A. Thus, although the data voltage of the same gray level is applied in FIGS. 3A and 3B, a display luminance in FIG. 3B is greater than a display luminance in FIG. 3A.
Second, as shown in FIG. 2, in the related art display device, a parasitic capacitance Cgs varies depending on an overlap degree between source electrodes and gate electrodes of the TFTs on odd-numbered display lines and even-numbered display lines. A kickback voltage ΔVp applied to a pixel voltage of the odd-numbered display lines is different from a kickback voltage ΔVp applied to a pixel voltage of the even-numbered display lines due to a deviation of the parasitic capacitance Cgs. As a result, the same pixel voltage is applied to the odd-numbered display line and the even-numbered display line, a hold voltage level of the odd-numbered display line is different from a hold voltage level of the even-numbered display line. This is perceived as 30 Hz flicker as shown in FIG. 4. This problem is applied to the interlaced low speed driving mode of the frame frequency less than 30 Hz as well as the frame frequency of 30 Hz. As the frame frequency is lowered, visibility of the flicker increases.